1. Field of the Invention
The present invention relates to a liquid crystal display (LCD), and more particularly, to a pixel structure of a liquid crystal display that prevents data bus lines and drain electrodes overlapping gate bus lines and gate electrodes respectively on an array substrate from opening.
2. Description of the Related Art
As modern society becomes a more information-oriented society, LCDs become more and more important to display information. The cathode ray tube (CRT) that has been most widely used in the past has many advantages, e.g., in performance and price, but it also has a lot of disadvantages, e.g. in miniaturization and portability.
While, an LCD may be more expensive than CRT or other displays, it has advantages such as miniaturization, low weight, a slim profile, and low power consumption to become an attractive substitute for the CRT display.
The LCD includes an array substrate on which thin film transistors are arranged, a color filter substrate on which red, green, blue color filter layers are formed and which is attached with the array substrate, and liquid crystal interposed therebetween.
The array substrate and the color filter substrate are formed by patterning and etching various layers by using a photolithography process. The array substrate may be fabricated as described below.
First, a metal layer is deposited on a transparent glass substrate and etched to form a gate bus line and a gate electrode (first masking step). After that, a gate insulating film, an amorphous silicon film and a doped amorphous silicon film are each coated on the glass substrate and etched to form a channel layer (second masking step). Next, a source/drain metal film is deposited on the glass substrate by which the channel layer is formed, and etched to form source/drain electrodes and a data bus line (third masking step). Afterwards, a passivation film for protecting the previously formed elements is deposited on the glass substrate and a contact hole is formed in the passivation film (fourth masking step). Thereafter, an indium-tin-oxide (ITO) transparent metal film is deposited on the substrate on which the passivation film is formed, and etched to form a pixel electrode (fifth masking step).
In general, five to eight masking processes are used in manufacturing an array substrate. Then, because increasing the number of masking steps causes the manufacturing cost to increase, recent research has lead to a reduction in the number of the masking steps in the LCD manufacturing process, so that a process in which a channel layer and source/drain electrodes are formed simultaneously results in four masking steps, and this process is now widely being employed.
To successfully perform the four masking step process described above, a photo resist film is patterned in half tone and etched using a half tone mask to simultaneously form a source electrode, a drain electrode, and an active layer region. In another method, when patterning a photo resist film, the photo resist film is exposed using a mask with a slit pattern having a resolution less than a normal resolution.
In four or five masking processes, a gate bus line and a data bus line formed on the array substrate are perpendicularly crossed and overlap each other. Here, a predetermined stepped portion is generated at the overlapped region due to the overlapped gate bus line.
Because this stepped portion may cause the data bus line and the source and drain electrodes to open in manufacturing the array substrate, pixel structures generated by various methods to prevent such an opening are being studied.
FIG. 1 is a plan view of the structure of an array substrate of an LCD according to the related art.
Referring to FIG. 1, a plurality of gate bus lines 1a and 1b and a plurality of data bus lines 3a and 3b cross substantially perpendicularly with each other to form a unit pixel region.
Thin film transistors (TFTs) which are a switching element are formed and arranged where the gate bus lines 1a and 1b and the data bus lines 3a and 3b intersect. Pixel electrodes 9a and 9b made of transparent ITO are arranged on unit pixel regions.
The gate bus lines 1a and 1b and the data bus lines 3a and 3b are arranged to overlap each other. A gate insulating film and an active layer 7 are interposed between the two lines. The data bus line 3a, a source electrode 6a, and a drain electrode 6b are arranged on the active layer 7.
The active layer 7 is formed of amorphous silicon layer and n+ amorphous silicon layer. In the TFT formation, the active layer 7 is formed as a channel layer and an ohmic contact layer.
A passivation film is formed on the data bus line 3a, the source electrode 6a and the drain electrode 6b so that the passivation film protects the elements formed on the array substrate. To connect the pixel electrodes 9a and 9b with the drain electrode 6b, contact holes are formed in the passivation film. Drain electrodes 6b are respectively connected to the pixel electrodes 9a and 9b through the contact holes.
The array substrate shown in FIG. 1 has a structure in which the active layer 7 is exposed by a predetermined width on both sides of the data bus lines 3a and 3b. The structure is formed by the four masking step process in which the source/drain electrodes and the channel layer are formed simultaneously.
Because the gate bus lines 1a and 1b and a gate electrode 5 arranged on the array substrate overlap the data bus lines 3a and 3b and the drain electrode 6b with the active layer 7 interposed therebetween, a stepped portion is formed at the boundary portion of the overlapped area.
This stepped portion of the overlap area may cause the data bus lines 3a and 3b to open or the drain electrode 6b to open. To prevent such an opening, a predetermined groove is formed on the gate bus lines 1a and 1b at a boundary area where the gate bus lines 1a and 1b overlap the data bus lines 3a and 3b. 
FIG. 2 is an enlarged view of the cross region (A) of the data bus line and the gate bus line shown in FIG. 1.
As shown in FIG. 2, a TFT is arranged on the area at which the data bus line 3a and the gate bus line 1a cross each other. The gate bus line 1a to which a driving signal is applied and the gate electrode 5 of the TFT are integrally formed and arranged.
The gate insulating film 4 (see FIG. 3) and an active layer 7 are formed on the gate electrode 5. The source electrode 6a and the drain electrode 6b overlap a predetermined portion of the gate electrode 5 on the active layer 7.
When the drain electrode 6b overlaps the gate electrode 5 and is contacted with the pixel electrode 9a, a stepped portion is formed due to the gate electrode 5 positioned at the lower portion of the drain electrode 6b. 
Likewise, a stepped portion is formed in the region where the gate bus line 1a and the data bus line 3a intersect with the gate insulating film 4 and the active layer 7 interposed therebetween.
As shown in the drawing, the reason why a groove 8 is formed in the region where the gate bus line 1a overlaps the data bus line 3a is to minimize the stepped portion of the gate bus line and thereby to prevent the data bus line 3a from opening. In other words, by forming a groove 8 in the gate bus line 1a, when a metal film is deposited to form the data bus line 3a overlapping the gate bus line 1a, the groove formed on the gate bus line 1a reduces the size of the stepped portion so that the metal film is deposited smoothly. However, in the pixel structure of the liquid crystal display, although the groove 8 is formed in the gate bus line, the data bus line may be opened due the stepped portion in the area where the data bus line 3a overlaps the gate bus line 1a. 
In addition, because the array substrate formed in the four masking step process has a lower active layer whose width is wider than the width of the source electrode 6a, the drain electrode 6b, and the data bus line 3a, penetration of etchant and pattern defects are caused, and thus the drain electrode 6b and data bus line 3a may be opened.
FIG. 3 is a cross-sectional view taken along the line B–B′ of FIG. 2.
As shown in FIG. 3, a gate bus line 1a is formed on a transparent insulating substrate 10. A gate insulating film 4 and an active layer 7 are sequentially deposited on the gate bus line 1a. 
The data bus line 3a is arranged along the active layer 7. The data bus line 3a has a predetermined stepped portion due to the gate bus line 1a, a stacked gate insulating film 4, and the active layer 7.
The cross-sectional structure is also formed in a region where the drain electrode and the gate electrode of the TFT overlap each other.
Although not shown clearly in the drawing, in the four masking step process as shown in FIG. 1, the width of the active layer interposed below the data bus line is wider than the width of the data bus line, so that the etchant may penetrate the data bus line along the active layer to thereby cause the data bus line to open.
To prevent the data bus line from opening, a predetermined groove is formed in the gate bus line, but in spite of the existence of the groove in the gate bus line, the stepped portion is still formed in the data bus line to cause the data bus line to open.